Presently known microprocessors have execution units which are used to perform arithmetic and logical operations on data and address information. Early microprocessors used a single arithmetic/logic unit to perform both types of calculations. Later generation microprocessors added one or more additional ALUs to independently perform operations on data and on memory addresses. One such MPU is the Motorola M68000 which had an execution unit partitioned such that three arithmetic operations could be performed simultaneously: data operations, memory address high (i.e., the most significant 16 bits of memory address), and memory address low. The parallelism which this allowed increased the speed of operation of the device.
In the M68000, the memory address sections of the execution unit calculated the addresses for both the data memory and the instruction memory. So while both high and low portions of an address could be simultaneously calculated, the instruction stream address and the operand (data) addresses were performed sequentially.
In the case of microprocessors intended to operate at high speeds, it is advantageous to perform as many operations as possible in parallel. This would be especially advantageous in the case in which a microprocessor has an on-chip high-speed instruction cache memory, the address for which is generated simultaneously with the operand addresses. Since an on-board cache may be accessed without reference to the MPU external bus, the operands can be accessed over the external bus while the next instruction is accessed from the cache.